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General Information

This is a page for Matt Jacobsen, Mike Rose and Patrick Lai

The FPGA code (verilog, C, etc.) is kept in the seed.ucsd.edu SVN server. To access the server, you'll need a user account on seed.ucsd.edu and a SVN client. Contact any member listed here to get an account. To get a SVN client, you can search for one that runs on your OS. There are several to choose from. When adding the SVN repository in your SVN client, the repository root URL is: svn+ssh://username@seed.ucsd.edu/data/fpga. The repository username and password correspond to your username and password on seed.ucsd.edu.

To check out the repository make sure you belong to the group fpga on seed and then issue the command

svn checkout svn+ssh://username@seed.ucsd.edu/data/fpga

Workstation Information

Model Dell Optiplex 745 Dell Optiplex GX620
OS Fedora 10 Fedora 10
hostname csevideodisplay4b.ucsd.edu freundlabpc4.ucsd.edu
FPGA xc5vsx50t n/a

Please contact Sunsern for account information.

VNC instruction

How To Use VNC

Lab Diaries

Clock Rates

The main clock rates used in our design are:

  • PLB_CLK = clock of the internal processor bus: 125MHz. 8 nano second clock cycle.
  • VGA_CLK = Clock driving the VGA display: ~25MHz. 40 nano second clock cycle.


Custom Core Integration with MicroBlaze Designs

Video converter


  • Datasheets and user guides for the SXT family of Virtex 5 chips and [FXT family]. According to these datasheet the BRAM is organized in 36Kbit blocks, each of which can be partitioned further into 2 18Kbit blocks (for both chips). Thus the minimal BRAM unit is 18Kbit or 2250 bytes. The XC5VSX50T (ML506 board) has 132 blocks of 36Kbits, totaling 4752Kb=594KB. The XC5VFX70T (ML507 board) has 148 such blocks 5238Kb=666KB.

A half-frame of video (640x240) is 460800 bytes. i.e. a very tight fit in either chip.

These BRAM blocks can be used by having Core Generator produce a specifically configured module or by instantiating RAMB primitives directly. Such RAMB primitives include RAMB36 and RAMB18. The Virtex-5 Library Guild for HDL Design is like an API specification for all Virtex-5 supported primitives (including the RAMB primitives). Search this pdf for RAMB and you'll see how to instantiate/use these primitives directly.

In addition, this document describes RAM primitives (Distributed RAM). Using these primitives makes use of LUT, not BRAM. There is much less of this resource than BRAM, but it is partitioned into smaller chunks. So if you only have a small amount storage need, this might be the right fit. A document describing which resource to use can be found here.



Digilent XUPV5

Product Page

  • Xilinx Virtex-5 XC5VLX110T FPGA
    • Includes 5,328 Kbit of BRAM, i.e. about 666 kilo bytes. One can also use logic blocks as "distributed RAM" up to a maximum of 1,120 Kbits.
  • Two Xilinx XCF32P Platform Flash PROMs (32 Mbyte each) for storing large device configurations
  • Xilinx SystemACE Compact Flash configuration controller
  • 64-bit wide 256Mbyte DDR2 small outline DIMM (SODIMM) module compatible with EDK supported IP and software drivers
  • On-board 32-bit ZBT synchronous SRAM and Intel P30 StrataFlash
  • 10/100/1000 tri-speed Ethernet PHY supporting MII, GMII, RGMII, and SGMII interfaces
  • USB host and peripheral controllers
  • Programmable system clock generator
  • Stereo AC97 codec with line in, line out, headphone, microphone, and SPDIF digital audio jacks
  • RS-232 port, 16x2 character LCD, and many other I/O devices and ports

Notes: This board's Virtex-5 (XC5VLX110T) has slightly more BRAM blocks than our current Virtex-5 (XC5VSX50T) and significantly more logic blocks. See Virtex-5 Family Overview for more information.

Reference Designs

Here is what Parimal Patel from Xilinx says:

There are no reference designs for XUPV5 available yet. You should be able to generate a design for ML505 (which is supported in EDK ) and then change the part to LX110t instead of LX50t, and it should work as the ucf file is same for the both.

Parimal Patel XUP Senior Systems Engineer

[ML505 Reference Designs]

FPGA Forums

Xilinx forum


General FPGA forum (Google Group)


Linux Development Environment

  1. Obtain ISE and EDK from the [Xilinx Download Site] (Professor Freund has the sign in credentials).
  2. Install ISE and EDK as specified in the install instructions.
  3. The Xilinx JTAG drivers don't work very well on Linux. Instead use the open-source JTAG drivers from [[1]].
    1. Build the library by running 'make'. If you are on a 64-bit system but want to build a 32-bit library, run 'make lib32' instead. You'll need 32-bit versions of libusb-devel and libftdi-devel installed!
    2. Put the following line in a new file "libusb-driver.rules" in /etc/udev/rules.d/ and restart udev: ACTION=="add", BUS=="usb", SYSFS{idVendor}=="03fd", MODE="666"
    3. If your cable does not have the ID 03fd:0008 in the output of lsusb, the initial firmware has not been loaded. To load the firmware follow these steps:
      1. Copy /path/to/ISE/bin/lin/xusbdfwu.rules to /etc/udev/rules.d/xusbdfwu.rules
      2. Install the package containing /sbin/fxload from your linux distribution. It is usually called "fxload".
      3. Copy the files /path/to/ISE/bin/lin/xusb*.hex to /usr/share/ and restart udev and re-plug the cable.
    4. To use this library you have to preload the library before starting impact by setting the environment variable LD_PRELOAD=/path/to/libusb-driver.so
  4. Before starting ISE or EDK you must 'source' the respective settings32.sh file located in the installation directory of ISE or EDK. To simplify things I usually just create a bash script that preloads the JTAG library, i.e. setting the environment variable LD_PRELOAD=/path/to/libusb-driver.so, then runs 'source' on the settings32.sh files before launching ISE or EDK.

  • *Note*: you don't need LD_PRELOAD for 11.1. However, your cable still needs to have ID 03fd:0008.

Problems and Solutions

  • How to start xps?
    • Before you can start xps, you need to set environment variables as follows.
source /opt/Xilinx/11.1/EDK/settings64.sh
source /opt/Xilinx/11.1/ISE/settings64.sh
source /opt/Xilinx/11.1/settings64.sh
  • xps_sdk doesn't start
    • Try java -jar /opt/Xilinx/11.1/EDK/eclipse/bin/lin64/startup.jar. Close it and try xps_sdk again.